The present invention is directed generally to digital equipment, and more particularly to apparatus for synchronizing transitions of an input signal to a transition of a digital clock signal in the form of a periodic pulse train within one period of the pulse train.
In digital systems, it is not unusual to control the transfer of data between independent units, such as a device controller and a peripheral device controlled thereby, using control strobe pulses or, as they are more usually called, "handshake" signals. Generally, a handshake signal will signify, for example, that a piece of data is present on the input/output lines connecting the peripheral device and its controller. The handshake can then be applied, along with a timing or clock signal (usually in the form of a periodic pulse train) to appropriate logic to effect proper data transfer (or other operations). In such circumstances, synchronization is desired, if not necessary, between the handshake and a clock to avoid generation of spurious signals.
Often, due to physical tolerances in the manufacture of the hardware used to control such systems, the relative position in time of the handshake signal and clock will vary over a range, even if the devices are driven in lock-step by a common clock. Such variations in the duration and timing of handshake signals cause problems where the handshake must be present in synchronism for the handshake to be recognized as valid.
More often, however, units that communicate with one another are synchronously operated by their own independent clocks so that the handshake signals between them appear asynchronously.
Further, because of the nature of presently known synchronizing circuits, synchronization cannot be achieved in less time than one clock period--even in a best case situation. However, in high-speed data transfers between, for example, a peripheral device and its corresponding controller, it is often necessary that data transfers occur in a time period that is no more than a clock period in order to prevent data overrun (i.e., incoming data overriding immediately preceding data). Data overrun problems can be cured by one of two methods: Adding more logic circuitry in the form of additional buffering (and multiplexing the incoming line to the separate buffers), or ensuring that the ultimate transfer of a first piece of incoming data is made before the immediately succeeding piece of data is lost (i.e., slow down the transfer rate). The former method adds expense and complexity to the system, the latter costs time.